The present invention relates to a DRAM, and more particularly to an 1-transistor type DRAM cell, a DRAM device and a manufacturing method therefore, a driving circuit for a DRAM, and a driving method therefor.
A representative device of a semiconductor memory device is a DRAM. The DRAM generally has a constitution configured of one transistor and one storage capacitor, wherein the constitution forms one unit cell. A digital data 1 (high) or 0 (low) is stored in the storage capacitor. In order to normally maintain a data level stored in the storage capacitor, the DRAM performs a refresh operation which is a recharge operation, while having a constant time interval. The DRAM having such a unit cell has been developed up to a synchronous semiconductor memory device referred to as a double data rate (DDR) SDRAM series (currently, developed up to a DDR3).
However, as the density of the DRAM progresses to giga-grade, the area of the chip should be larger. This will be acted as a burden in view of a system that as the chip size becomes smaller, it has an advantage.
In order to this burden, one of the proposed methods is the 1-transistor type DRAM allowing the unit cell to be configured of only one transistor by removing the storage capacitor. The 1-transistor type DRAM is also referred to as a capacitor-less type DRAM.
FIG. 1 is a cross-sectional view showing a cross section constitution of a unit cell structure of an 1-transistor type DRAM according to the prior art. The constitution of FIG. 1 indicates a floating body cell or floating channel cell with a silicon on insulator (SOI) structure. As shown in FIG. 1, data are stored by storing holes and electrons on the floating body.
FIG. 2 is a view showing a flow process of a read current and a cell data storing state of the 1-transistor DRAM according to the prior art. In FIG. 2, 2A is a Store “1” which is a state storing a data 1, wherein the Store “1” state is a state where there are many holes in the floating body. In FIG. 2, 2B is a Store “0” which is a state storing a data 0, wherein the Store “0” state is a state where there are a few holes in the floating body or there are many electrons therein. In FIG. 2, 2C indicates a flow of a read current, wherein in a read mode, more sensing current in a cell current flows in the store “1” than in the store “0”. In FIG. 2, a line connected to the gate of the transistor is a word line and each of lines connected to both channels of the transistor indicates a sensing line and a bit line.
FIG. 3 is a waveform view showing waveform characteristics of a cell read current of the 1-transistor type DRAM according to the prior art. In FIG. 3, when a cell drain voltage Vd is 0.2V and a cell source voltage is a ground GND, there is shown a cell read current at the time of sweeping a cell gate voltage. As shown, the read current is largest in the Store “1” and smallest in the Store “0”, and a reference (REF) current is located in the middle thereof.
As such, the floating body DRAM cell with the 1-transistor structure of the prior art does not destroy the cell data by means of a non destructive read out (NDRD) manner when performing a read operation, making it possible to improve the reliability of the cell and the read speed. Also, since the cell is configured of only the 1-transistor, the cell size can remarkably be reduced.
However, the following problem occurs when reading information on the cell and writing information in the cell. In other words, when writing the information, as a write voltage is applied to the selected cells as well as the non-selected cells, the problem that the data of the non-selected cells are destroyed occurs. The reliability of the semiconductor memory device cannot be assured due to this problem.
Meanwhile, when implementing a semiconductor device by applying the SOI wafer, it is advantageous in view of the device characteristics; however, it is not preferable in view of productivity since the SOI wafer is more expensive than a general silicon wafer.
In particular, when manufacturing a semiconductor device by applying the SOI wafer, the existing equipments and processes are designed to be suitable for the case applying the silicon wafer. Therefore, when manufacturing the semiconductor device by applying the SOI wafer, there are the problems that the modification and development of the manufacturing equipments and processes are also required.